Easyi3C is a leading supplier of embedded system tools that simplify the development and debugging of various communication protocols. The company offers a range of products designed to help engineers and developers use I3C/I2C , USB and MIPI, JEDEC, MCTP and other protocols more efficiently.

14. Tower Console I3C/I2C Protocol Generator (5)

Based on continuous customer feedback, we have developed a unique, graphical I3C/I2C Protocol Generator. Its GUI allows for the easy insertion of spikes and the adjustment of duty cycles and various I3C/I2C timing parameters; it offers powerful functionality and far superior ease of use compared to DTG, enabling customers to conduct more professional and effective I3C/I2C protocol testing.

5 Component Parameter Editing

Double-click a protocol block in the track to open its parameter editing dialog. Different component types support different parameters.

5.1 Component Spike Settings

Some components support Spike settings, including Start, Repeat Start, Stop, Addr, Write Data, Write Bit,

After double clicking:

a)      Spike Line Options

Spike Line supports the following options:

When Spike Line is None, the Spike input field is hidden or ignored, and the saved Spike value becomes None.

b)      SDA / SCL Spike Format

When Spike Line is SDA or SCL, the Spike format is:

[['20%', 10]]

Meaning:

Insert a 10ns spike at the 20% position of the component.

Multiple Spike example:

[['20%', 10],['30%', 20]]

Meaning:

Insert a 10ns spike at the 20% position of the component,

Insert a 20ns spike at the 30% position of the component.

c)      ALL Spike Format

When Spike Line is ALL, two formats are supported.

Format 1: Same Spike Setting for SDA and SCL

[['20%', 10],['30%', 20]]

Format 2: Separate Spike Settings for SDA and SCL

[[['10%', 10],['30%', 20]], [['20%', 10],['30%', 20]]]

The outer list must contain exactly two lists, representing two groups of Spike settings.  The first list is SDA spike, the second list is SCL spike.

d)     Spike Validation Rules

Each Spike item must follow this format:

[['position%', width]]

Validation rules:

5.2 Component Duty Cycle Settings

Duty Cycle supports different formats for different components.

a)      Simple Duty Cycle Format

For signal-level components such as W, R, and Write Bit, Duty Cycle can be:

After selecting ok, it may be displayed as:

For W / R, Duty Cycle must be an integer from 1 to 99, or None.

b)      Addr, Write Data, Read Data Duty Cycle Format

Addr supports bit-based Duty Cycle settings follow this format:

[[bit number, duty cycle]]

Example:

[[1, 10]]

Meaning:

It means that bit1 in one clock cycle the scl high percent is 10%.

[[1, 10], [3, 40]]

Meaning:

It means that bit1 in one clock cycle the scl high percent is 10%,

It means that bit3 in one clock cycle the scl high percent is 30%.

Validation rules:

After selecting ok, it may be displayed as: