Easyi3C is a leading supplier of embedded system tools that simplify the development and debugging of various communication protocols. The company offers a range of products designed to help engineers and developers use I3C/I2C , USB and MIPI, JEDEC, MCTP and other protocols more efficiently.
PMIC is a very important chip introduced in DDR5. Before that, DRAM was directly powered by the motherboard. The advantage of this was that the memory was relatively simple, but it brought a lot of instability in actual applications.
With the advent of DDR5, memory has higher requirements for power supply stability, which has forced memory manufacturers to seek a more stable and reliable power supply method. DDR5 PMIC has thus become part of the JEDEC standard.
PMICs offer numerous advantages, such as providing more stable power supply, isolating the power supply between the motherboard and memory, and managing it through a single PMIC node. Furthermore, PMICs possess many functions, including precise configuration of the voltage of each power output, write protection, overload protection, and various error detection mechanisms. This allows PMICs to provide users with greater customization possibilities while ensuring stable and safe power supply.
As explained above, access to the PMIC chip on DDR5 memory is via the I3C/I2C protocol. This necessitates additional testing for the chip using the I3C protocol, introducing new testing requirements such as testing CCC commands, IBI, and PEC. The Tower I3C Host Adapter can easily meet these testing needs. We can perform debugging and verification using diagrams similar to the one shown below, easily verifying the chip's various functions, providing timely feedback to the design and development team, and shortening the chip's development cycle.
To facilitate testing of DDR5 devices, we have provided dedicated APIs for DDR5 PMIC, encapsulating complex protocols within these APIs for easy user adoption. Our APIs fully comply with the JEDEC JESD403-1 standard. The relevant APIs are as follows:
For more detailed information, please loginin Easyi3C Visit the official website to download and learn more for free.
Using the APIs provided above, we can build automated test scripts to meet different needs, making it convenient to test various functions. Below is a code example:
# ==========================================================================
# --------------------------------------------------------------------------
# Copyright © 2025 by Easyi3C, Inc.
# All rights reserved.
# --------------------------------------------------------------------------
# ==========================================================================
import sys
from ezi3c.api import *
from ezi3c.utils import hex_string
from ddr5 import Pmic0
ez = ez_open()
if not ez:
print("Cannot open Adapter")
sys.exit(-1)
clk = ez_set_bus_clk_freq(ez, 1000, 4000)
print("Cur Clk Freq: {}".format(clk))
ret = ez_set_io_voltage(ez, 1.0)
assert ret == 0, "Faield to set IO voltage"
pmic = Pmic0(ez, hid=0x00)
reg = 28
try:
ret = pmic.ccc_rstdaa()
assert ret == 0, "Failed to reset DAA: addr:{:02X}".format(pmic.addr)
ret, data = pmic.i2c_read_reg(0, 2)
assert ret == 0 and data == (0x80, 0xB3), "Failed to read PMIC data: addr:{:02X}".format(pmic.addr)
print("PMIC Data: {}".format(hex_string(data)))
pmic.switch_to_i3c(send_ccc=True)
ret, data = pmic.i3c_read_reg(0, 2)
assert ret == 0 and data == (0x80, 0xB3), "Failed to read PMIC data in I3C mode: addr:{:02X}".format(pmic.addr)
ret = pmic.i3c_write_reg(reg, 0xC0)
assert ret == 0, "Failed to write to PMIC register: addr:{:02X}".format(pmic.addr)
ret, data = pmic.i3c_read_reg(reg, 1)
assert ret == 0 and data == 0xC0, "Failed to read PMIC register after write: addr:{:02X}".format(pmic.addr)
print("write read with IBI header")
ret = pmic.i3c_write_reg(reg, 0xb0, with_ibi_header=True)
assert ret == 0, "Failed to write to PMIC register: addr:{:02X}".format(pmic.addr)
ret, data = pmic.i3c_read_reg(reg, 1, with_ibi_header=True)
assert ret == 0 and data == 0xb0, "Failed to read PMIC register after write: addr:{:02X}".format(pmic.addr)
print("Inject parity error test")
ret = pmic.i3c_write_reg(28, 0xF0, inject_parity_err=True)
ret, data = pmic.i3c_read_reg(28, 1)
assert ret == 0 and data == 0xb0, "Failed to read PMIC register after write: addr:{:02X}".format(pmic.addr)
ret = pmic.i3c_write_reg(28, 0xF0)
assert ret == 0, "Failed to write to PMIC register: addr:{:02X}".format(pmic.addr)
ret, data = pmic.i3c_read_reg(28, 1)
assert ret == 0 and data == 0xF0, "Failed to read PMIC register after write: addr:{:02X}".format(pmic.addr)
print("Enable PEC then read write register test")
ret = pmic.enable_pec(send_ccc=True)
assert ret == 0, "Failed to enable PEC: addr:{:02X}".format(pmic.addr)
ret, data = pmic.i3c_read_reg(0, 1)
assert ret == 0 and data == 0x80, "Failed to read PMIC data in I3C mode with PEC: addr:{:02X}".format(pmic.addr)
print("PEC inject error")
ret, data = pmic.i3c_read_reg(0, 1, inject_pec_err=True)
assert data is None
ret = pmic.i3c_write_reg(28, 0xF0)
assert ret == 0, "Failed to write to PMIC register: addr:{:02X}".format(pmic.addr)
ret, data = pmic.i3c_read_reg(28, 1)
assert ret == 0 and data == 0xF0, "Failed to read PMIC register after write: addr:{:02X}".format(pmic.addr)
print("Disable PEC then read write register test")
ret = pmic.disable_pec(send_ccc=True)
assert ret == 0, "Failed to enable PEC: addr:{:02X}".format(pmic.addr)
ret, data = pmic.ccc_getstatus()
assert ret == 0, "Failed to get CCC status: addr:{:02X}".format(pmic.addr)
print("CCC Status: {}".format(hex_string(data)))
ret, data = pmic.ccc_devcap()
assert ret == 0 and data == (0x04, 0x00), "Failed to get Device Capabilities: addr:{:02X}".format(pmic.addr)
print("Device Capabilities: {}".format(hex_string(data)))
print("Disable PEC")
ret = pmic.disable_pec(send_ccc=True)
assert ret == 0, "Failed to enable PEC: addr:{:02X}".format(pmic.addr)
print("Two Byte address Test")
ret = pmic.i3c_write_reg(0x30, 4) # slave enter two Byte mode, need change according your chip
assert ret == 0, "Failed to enter two Byte mode addr:{:02X}".format(pmic.addr)
ret, data = pmic.i3c_read_reg(0x300, 1)
assert ret == 0, "Failed to read two Byte mode: addr:{:02X}".format(pmic.addr)
print("PMIC two Byte addr: {:02X} Data: {}".format(0x300, hex_string(data)))
print("Two Byte address Test with PEC")
ret = pmic.enable_pec(send_ccc=True)
assert ret == 0, "Failed to enable PEC: addr:{:02X}".format(pmic.addr)
ret = pmic.i3c_write_reg(0x30, 4) # slave enter two Byte mode, need change according your chip
assert ret == 0, "Failed to enter two Byte mode addr:{:02X}".format(pmic.addr)
ret, data = pmic.i3c_read_reg(0x300, 1)
assert ret == 0, "Failed to read two Byte mode: addr:{:02X}".format(pmic.addr)
print("PMIC two Byte addr: {:02X} Data: {}".format(0x300, hex_string(data)))
ret = pmic.disable_pec(send_ccc=True)
assert ret == 0, "Failed to enable PEC: addr:{:02X}".format(pmic.addr)
finally:
pmic.ccc_rstdaa()
ez_close(ez)
print("Adapter closed.")Based on our Tower I3C Host Adapter, DDR5 PMICs can be tested very easily, meeting complex testing needs, building automated testing environments, and shortening chip time to market.
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